Every data processor or, as variously termed, computer system, contains at least one communications bus, often simply referred to as a system bus or, simply, bus, by means of which information in digital form, whether data and/or control information, is transferred by and between various component and peripheral elements of the computer system. In a computer system having a plurality of computer devices coupled over a system bus, such as a central processing unit and an internal memory unit, as example, an orderly system must be provided to achieve bi-directional transfer of digital information between such devices. When such computer devices include, for example, one or more central processor units, CPUs, and various types of peripheral device interfaces, such as magnetic tape storage devices, disk storage devices, electronic memory and the like, as may be referred to generically as computer resources or devices coordinated efficient transfer of digital information among those elements require coordination that is regarded as somewhat complicated.
A typical communication bus in such a prior computer system contains essentially three parts: address, data and control bus portions, as logically define the types of information transmitted over the bus. The communication bus may be of a serial type, in which data and control information is transmitted serially or it may be of a parallel type, the latter of which concerns the present invention. The data and address portions are usually parallel buses, wherein the address and data information are each propagated as a group of digital "bits" in parallel, as forms a digital "word". The word in turn defines an address within the computer resource or data information or portions thereof. Each such parallel bus thus is said to be of a certain number of digital bits in width. As example, a bus structure capable of processing thirty-two bit length digital "words" may contain at least thirty-two electrical lines or leads for data information and may frequently contain thirty-two additional leads for address information; those kinds of information can be transmitted simultaneously, in parallel. Some systems cause address and data to share a common bus, each being allotted a time slot so that first address and then data traverse the same lines.
Each communications bus includes control lines or a control bus portion, as variously termed. The control lines carry the signals that manage the direction of data transmission from source to destination; the acquisition and relinquishment of control of the bus in those systems containing more than one central processing units or "master"; processor "interrupts" from one card to another; power-up and down sequencing; bus errors, which may occur, data error detection and correction; sequence control information and the like. In these control functions the design of one computer may differ from that of another computer design. Consequently, as between computer designs the control bus is subject to significant differences in size and function, the number of electrical leads forming the bus and their purpose, depending upon the desired bus characteristics for a particular computer. In that regard the composition of the control bus in the present invention contains unique features: lines are included that carry the identification of the particular computer resource within the computer system that accessed the communication bus.
Interconnections between the computer resources of a computer system range from those having common data bus paths, as previously discussed, to those which have special transmission paths. Some such systems require the data processor's control of any data transfer on the bus even though, for example, the transfer may be between devices other than the data processor and be independent of the manner in which such devices are connected or operate. Other more efficient systems employ a separate state machine or processor, a controller, dedicated to management and control of the communications bus, thereby relieving the central processor unit of that burden. The processor associated with a particular computer resource need only take the time to drop off instructions and data to the bus controller and returns immediately to its other tasks. In turn the bus controller performs all the tasks necessary in the system to carry out those instructions and controls the communications bus. The present invention likewise employs a unique controller or interface, as variously termed, to control the communications bus.
Prior computer systems may include capability for either synchronous or asynchronous operation in combination with the particular communication bus. In general, data buses used in such systems are either synchronous, wherein data transfer is performed in synchronization with a clock signal, or are asynchronous, wherein handshake signals synchronize the sending and receiving units. The present invention includes a combination of both characteristics, allowing for operations synchronously and requiring handshakes, asynchronously given, to acknowledge receipt of data transmitted on the bus.
In a synchronous data bus system, all data transfers are performed in synchronization with a clock signal. That is, the operation of the sending and receiving units is synchronized to the system clock, wherein operation occurs, for example, on the rise of the clock pulse at the beginning of each clock cycle. Such systems may utilize either a single frequency clock, or a multiple or variable frequency clock. A single frequency clock system allows the use of simple clock circuitry. However, data transmission rate, and thus operation of the overall system, is limited to the data rate of the slowest device in such data processing system. In a multiple or variable clock rate system, a clock rate is selected to be that of the slower of the sending or receiving units currently communicating. Data rate may, however, be selected to be the highest achievable with the particular units which are communicating. A multiple or variable data rate synchronous system is, in general, more complex than a single clock rate system since the clock circuitry must be capable of generating a multiplicity of clock frequencies. Before data communication can be performed, however, the sending and receiving units must communicate to elect a clock rate. The present invention provides for transfer of digital information synchronously with a system clock of fixed frequency.
In an asynchronous data bus system, transfer of data between a sending and a receiving unit is effectively synchronized by handshake signals. That is, a sending unit places data on the bus and transmits a handshake signal to the receiving unit indicating that data is present on the bus. The sending unit then waits. When the receiving unit is ready it accepts the data and then transmits a return handshake signal to the sending unit, acknowledging that the data has been accepted. An asynchronous data bus system thereby allows greater flexibility of data rate. The data rate occasionally may be the maximum achievable rate between a particular sending and receiving unit pair.
An asynchronous data bus system is in general, however, more complex than a synchronous system due to the requirement to exchange handshake signals. In addition, maximum data rate may not be achievable due to the requirement to resynchronize the data transferred at the sending and receiving units. That is, data must first be transferred from one computer resource, for example, a disc drive, to a sending unit, then from the sending unit to the receiving unit, and finally from the receiving unit to, for example, a data processor. Additional delays in data transmission may be imposed at the sending end of the bus in transferring data from the peripheral device to the sending unit, and from the sending unit to the communications bus. This delay occurs because data transfer between the peripheral device and the sending unit is not synchronized with transfer of data from the sending unit to the data bus. Similarly, additional data transmission delays may be imposed at the receiving end because reception of data by the receiving unit is not synchronized with transfer of data between the receiving unit and the data processor. The present invention also uses a handshake signal, sometimes more properly referred to as an acknowledgement, to indicate the receiving computer resource's acceptance of digital information. However, with the present invention inefficiencies attendant to waiting on the bus for the handshake signal are avoided.
A prior digital data bus system that operates synchronously with a fixed clock rate and has a variable data rate selected by the sending and receiving units is presented in a prior patent U.S. Pat. No. 4,229,792 granted Oct. 21, 1980 to Jensen, et. al., entitled "Bus Allocation Synchronization System". As example, in that prior system a master controller is located, for example, at a data processor and a peripheral controller is located at each other unit, or peripheral device, of the data processing system. Peripheral devices may include, for example, processors, disc drive memories, intelligent terminals, or further data transmission links. The master controller and all peripheral controllers are interconnected through a communication bus. The master and peripheral controllers comprise the interfaces between, respectively, the data processor and peripheral devices and the bus. A fixed frequency clock is generated by the master controller and that clock is distributed to all peripheral controllers through a single clock line. In addition to address/data lines, the bus includes a single handshake signal line, referred to as the Hold line, shared by the master and peripheral controllers.
In that prior system all data transfers are executed on a clock pulse, i.e., synchronously, but data transfer rate is controlled by the particular sending and receiving units. A sending unit places digital information, for example, an address or data, on the bus in synchronization with the clock. If the receiving unit happens to be ready at that moment to receive that information, the information is transferred into the receiving unit on the same clock pulse. If the receiving unit, however, is not ready to receive the digital information on the bus, the receiving unit asserts a Hold signal on a Hold line. The sending unit responds to a Hold signal by maintaining the information to be transferred on the bus for each clock period in which Hold signal is asserted. When the receiving unit is ready to receive the information, the Hold signal is terminated and the information is transferred on the next clock pulse. Thus, all information transfers are synchronous with the single frequency, fixed period clock. Actual rate of data transfer, however, is variable and is automatically determined by the particular sending and receiving units so as to occur at the maximum rate achievable by the particular pair of sending and receiving units. In that system the effective "thruput" of information transfer on the communication bus as a practical matter would be limited as occasioned by routinely occurring "holds" tying up the bus. A hold requires all resources in the system to wait until the occurrence of a pre-defined event. No data is transferred. As that presents inefficiency, the present invention preferably does not include a hold. As distinct from a hold, a bus "lock" as enables a particular computer resource to control and use the bus is employed on a non-routine basis; the bus lock permits continued data transfer over the bus while "locked", thereby maintaining bus efficiency.
Every processor communication bus has a maximum theoretical limit to the amount of data that may be passed from one computer resource to another over the bus; a limit that is often referred to as "thruput". For example, a computer bus for a small computer having a thirty two bit wide data word might achieve a maximum thruput on the order of between twenty to forty million bytes per second, a "byte" comprising eight "bits", when using a clock of twenty five MHz. That thruput is not presently achieved with present day small computers due to the inability of the computer's main memory to support bus accesses faster than ten to twenty megabytes per second and also due to the presently existing direct link of the bus's thruput to the memory access time. Other less significant aspects of the computer structure also reduce actual system thruput, which are known and need not be here described in detail. In present practice, therefore, a typical small or medium size computer seldom moves more than one to ten megabytes per second of thruput; most move substantially less than one megabyte with occasional bursts of larger amounts. This results in a communication bus "thru-put" efficiency of under five percent. The present invention increases that efficiency. With the present invention, efficiencies of fifty percent up to one hundred percent of the theoretical thruput for the communications bus may be achieved during normal operation.
As further background to the present invention, the patent to Cassarino, et. al. U.S. Pat. No. 3,997,896, granted Dec. 14, 1976, illustrates a data processing system in which computer elements of the system communicate over a common bus in an arrangement that could provide enhanced thruput and higher communication bus efficiency. In Cassarino's data processor system a plurality of computer resource units may transfer information along a common bus using a priority scheme in which the unit having the highest priority may transfer information during an asynchronously generated "bus transfer cycle". Logic circuits are provided for enabling a split bus cycle operation, in which a "master" unit requesting information from a "slave" unit during a first bus transfer cycle may receive such information from the slave unit via the bus during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time interval between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of computer resource units to communicate with each other, respectively, in an interleaved manner. That "split bus cycle" form of operation thus enhances the efficiency or thruput of the communications bus, allowing intervening bus accesses by other computer sub-systems within the computer system, while the first sub-system is waiting for its response.
The architecture in Cassarino's computer system allows each master to access the communications bus for a complete "transfer cycle" as permits the master to maintain its access to the communications bus for several clock cycles, that is to hold onto the line for as long as it takes to effect the transfer of information. Further, the computer architecture in Cassarino precludes the possibility for the master and slave units that accessed the bus, awaiting completion of the request and acknowledgment from the slave, from communicating with other master or slave units during the intervening waiting period. Those aspects to the system architecture in Cassarino effectively limits the computer system's speed.
Accordingly, a principal object of the present invention is to speed up data processors by providing a computer system with a more highly efficient communications bus. A further object of the invention is to enhance operational effectiveness of a computer system by minimizing any standby or dwell periods in which the communications bus is being held by a subsystem and not being used for the transmission or reception of digital information, precluding access to other subsystems that may be waiting for access to the bus, and by limiting any access to the bus in normal operation to a fixed duration. And an additional object of the invention is to improve upon existing data processor systems by incorporation of a control means that effectively manages use of the communications bus to achieve greater utilization efficiency, allowing the digital "pipe-line" to be filled with information essentially at all times.